V L S I conference 2009 held at Taj Palace, New Delhi,
between Jan 5th and 7th 2009.
Hi People,
I am just jotting down few interesting things, high lights and key take away which I could attend, analyze and understand in the VLSI conference 2009 held at the Capital Delhi between 5th and 7th January 2009.
Apart from attending technical paper sessions I could listen to keynotes by tech gurus, meet few fellows in person, panel discussion sessions, interact with old buddies and a bit of sight seeing and yep, some good food at Taj!
It would be tough to share all the technical papers and hence my focus would be on key notes and other technical discussions. All in all, these things will fit into to my non volatile memory!!
Tamasoma jyothirgamaya (from the darkness towards the light), yeah… the inauguration on the foggy Monday morning said the same! What better talk would be than about VLSI itself; Improving Productivity was the theme of this conference. We had a brief discussion about the change in technology which is now tending towards memristors [resistor with memories]. More information can be excerpted from IEEE spectrum.
It was then Abhi Talwalkar, CEO-LSI and an X-intel who snatched the show by talking about the India’s Relevance in Semiconductor industry. He talked about the brief history of semiconductor business which started with some MNCs’ out sourcing 3rd party work and then large MNCs investing in India and then Indian companies expanding to become a software critical and a design centric corporate. He also discussed on the need of foundry and CAD growth. He called it off by saying a powerful note; Innovation has strategy!
I had to choose between Mixed signals and platform based design; A deep dive into technicalities indeed! Willy Sansen discussion on Analog IC design in nm CMOS explored the strength of analog circuits and the need to take it to next level. The solutions which he calls it as ‘circuit tricks’ for the issues like noise, distortion, voltage realization, gaining the ‘gain’ we discussed. We understood that, choosing a ‘right’ circuit is what makes the design excel after discussing the pros and cons of various analog devices and circuits. He started this piece of discussion by comparing telescopic cascode OpAmps, symmetric differential OpAmps, Folded cascodes and 2 staged OpAmps with compensation feedbacks. His opening comment was teasing! ‘…unlike the last session held, I will be technical, bare with me ;-)’
Vivek De, Intel Sr. Principle Engineer was on the keynote session- discussed about the 80 core project. Some open ideas on smart-FIFO, adaptive snoozing was discussed. I could get a chance to talk to him with Sunit Tyagi, Intel in the tea break. As most of the keynote sessions starts with the Moore-law mantra, we had another guru backing it up!
Rob Aiken, A fellow from ARM, talked all about DFx and productivity. He questioned about the cause of the DFY (Design For Yield), be it to take up DRC seriously, layout stability or power management in memory architecture. He described the fight for DFx at the well known interests viz. area, power, and performance for high yield, manufacturability and testability. He cautioned us to not to take the identical behavior of the adjacent transistors while going lower on the nm technology. To summarize, it was a good insight on the productivity with some nice photo show about cars which was commuting in each and every foil he had!
Another true follower of Moore and his law! It was Dr.Vivek Singh this time talking about lithography. He is Intel Fellow. Vivek talked about the nomenclature of the processes at Intel – p1266, p1268… and also gave the idea and importance of the tick-tock process. He neatly explained the techniques in lithography by giving an analogy to the camera. Though, few things were kept confidential he described about the dry and wet lithography, briefed the process involved to deal with the creation of the devices which are much smaller than the wave length of stencil light, and that he calls his bread winner!
A panel discussion worth to attend, fight and participate. The topic was provoking- “EDA Made-in-India: Fact or Fiction?” Some teasing questions to the EDA world in India- Is there enough momentum in innovation by EDA companies in India? Will we ever
see a “Made-in-India” tag for EDA products and services? We need to take few questions with a pinch of salt as the current EDA industry is tending towards the topics that affect manufacturing and yield, such as DFM, SSTA etc. Such topics warrant a deeper understanding of the Semiconductor process technologies and physics of deep-submicron devices. Given that Indian Semiconductor industry is mostly design oriented, with minimal experience in IC fabrication, will the EDA industry be curtailed in it’s growth? Still the EDA tycoons could justify that all these are possible at Indian EDA companies too.
Jacob Abraham from the University of Texas talked about the challenges at DSMs (Deep Sub Micron) designs. This was a perfect classroom session. Every statement of his was thoughtful. Can we have a comprehensive system to ‘completely test itself’? he discussed about the approach taken for Intel functional BIST, testing small delay defects, path delay vector generation with that knocking down about 91% [adhere to the a certain process technology] of sub paths for vector generation. His appreciations towards SoC and platform based design. His concluding thought was definitely an eye opener. If we assume that 20 transistor can build an equivalence neuron cell, The Pentium machine obviously has more neurons than an ant! But, can Pentium find its prey, search for shelter and defend itself? Why are we only running behind increasing computational domain? Why not the intelligence and make it more ‘human-like’. Was he tying or bridging A.I and VLSI? Not to sure, but he quoting that ‘Any community is a natural example for a true distributed system’ was amazing!
It was time for Thomas W Williams to take up the stage; he is a Fellow from Synopsys.
To mention his quote, “I can only sell electrons… talk to our sales team for other questions”, it was crazy of him to act drunkard showing the state of the electron in the resistive material. The questions were thrown to the audience whether to continue to use Cu for wiring? He talked about the future of EDA and its role in power management, area management and working on DRCs.
Neil Anderson from Mentor Graphics did the keynote on Standardization and Dr. Gary Delp from LSI joined him talked about a niche area “Making sense out of the potential babble of low power standards”. Again a controversial code “corruption is good thing only if you know where it is happening!” again he emphasized on SoC design, power management with nice trade off graphs, forcing power constraints at the architecture level and then he lead his way to the next session after describing about the evolution of various power formats. It was time for Steven Belly from Mentor graphics to continue the session talking about the details of Unified Power Format 2.0; I couldn’t get many things out of it though…
After good paper presentations from Prof. Saluja, we got into another session by Dr. Ajay Bose, founder of Atrenta. The topic was “Taming Soc design through Abstraction- what the past has taught us about the future.” It all started with an analyzing discussion about what are the driving forces for SoC design? Is it the economics or the business trends and the emerging solutions for all the creeping issues; some of the proposed design solution strategies proposed are abstraction, maintaining hierarchical designs, reuse, arch level optimization. He emphasized on the the advantages of using I.P.s he gave a overall business picture showing an ideal tandem functioning between System Company and Silicon Company. He quoted Gartner – “82% of 2012 SoC are from platform based designs”
Yet another panel discussion! What a teasing question – “Design Automation and reuse of analog designs increasingly trailing the digital world”. This session was chaired by Atul Jain from TI, Dallas. And the panel participants were Kamal Jain (Cadence), Abhijeet (Rambus), Sumit (Magma), Mc Grath (LSI), Seetharaman (Synopsys). Lot of argument happened here. Some supporting EDA, CAD and DA and some saying it is impossible to use automation for analog designs as used in digital. To back it up there was a nice quote - “Analog designs an art more than a science”. To summarize the panel accepted that EDA cannot take control of analog world as it has done with the digital world; all the EDA companies are researching to come up with automation and robust analog design libraries. Also, it’s a drive to change the mindset of analog designers. To wrap up, it was an humble request from DA world to analog engineers – “… designers… don’t give up hope on the EDA world!”
And then, few more tech paper attendance and I had to rush to the airport. The flight delay made me to pen down all these in an ascii format! Talk to me or mail me if you want to know more about all these and the technical paper CD, I hope I can give you what you want! Also, feel free to forward this for the relevant.
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